The invention relates to an amplifier circuit for adding a Laplace transform zero to a linear integrated circuit, and more particularly to an amplifier circuit for adding a Laplace transform zero in a switching regulator feedback loop for providing frequency stability.
Closed loop negative feedback systems are commonly employed in linear integrated circuits. For instance, switching regulators use a feedback loop to monitor the output voltage in order to provide regulation. To ensure stability in any closed loop system, the Nyquist criterion must be met. The Nyquist criterion states that a closed loop system is stable if the phase shift around the loop is less than 180 degrees at unity gain. Typically, a compensation circuit is added to a feedback loop to modulate the phase shift of the feedback loop to obtain stability.
The frequency response of a linear circuit can be characterized by the presence of xe2x80x9cpolesxe2x80x9d and xe2x80x9czeros.xe2x80x9d A xe2x80x9cpolexe2x80x9d is a mathematical term which signifies the complex frequency at which gain reduction begins. On the other hand, a xe2x80x9czeroxe2x80x9d signifies the complex frequency at which gain increase starts. Poles and zeros on the left half plane of a complex frequency plane or s-plane are considered normal and can be compensated. However, poles and zeros on the right half plane of a complex frequency plane are usually problematic and difficult to manipulate and is not addressed in the present application. Generally, a pole contributes a xe2x88x9290xc2x0 phase shift while a zero contributes a +90xc2x0 phase shift. A pole cancels out the phase shift of a zero for zeros in the left half plane. In designing a closed loop system with compensation, the location of the poles and zeros are manipulated so as to avoid a greater than 180xc2x0 phase shift at unity gain.
In a linear circuit, poles are created by placing a small capacitor on a node with a high dynamic impedance. If the capacitor is placed at a gain stage, the capacitance can be multiplied by the gain of the stage to increase its effectiveness. Each pole has a zero associated with it. That is, at some point, the dynamic resistance of the gain stage will limit the gain loss capable of being achieved by the capacitor. Thus, a zero can be created by placing a resistor in series with the gain reduction capacitor.
A conventional voltage mode switching regulator uses an inductor-capacitor (LC) network at the voltage output terminal for filtering the regulated output voltage to produce a relatively constant DC output voltage. FIG. 1 is a schematic diagram of a conventional switching regulator including a switching regulator controller 10 and an LC circuit 11. Switching regulator controller 10 generates a regulated output voltage VSW at an output terminal 13 which is coupled to LC circuit 11 for providing a filtered output voltage VOUT. The output voltage VOUT is coupled back to controller 10 at a feedback (FB) terminal 15 for forming a feedback control loop. The LC circuit has associated with it two poles, one pole associated with each element. If the feedback control loop is not compensated, LC circuit 11 alone contributes an xe2x88x92180xc2x0 phase shift to the system and loop instability results, causing the output voltage to oscillate. Because virtually every switching regulator uses an LC filter circuit to filter the regulated output voltage, compensation must be provided in the feedback control loop of a switching regulator to compensate for the effect of the two poles introduced by the LC circuit.
A conventional compensation technique in switching regulators involves adding a circuit in series with the feedback loop which produces a Laplace zero. The zero is added to the feedback control loop to cancel out one of the two poles of the LC filter circuit, thus insuring closed loop stability. U.S. Pat. No. 5,382,918 to Yamatake describes using a capacitance multiplying op-amp to provide a large effective capacitance and a resistor in series as the frequency compensation element of a switching regulator. U.S. Pat. No. 5,514,947 to Berg describes a phase lead compensation circuit for providing additional phase to the loop gain of a switching regulator near the unity gain frequency. The phase lead compensation circuit of Berg uses a transconductance amplifier driving a frequency-dependent load, implemented as a band-limited op amp, in the feedback control loop of the switching regulator. These approaches are problematic because they both require a xe2x80x9chigh qualityxe2x80x9d differential amplifier in operation which is significantly large and complex to realize. In practice, differential amplifiers are typically large devices and can be relatively slow. Furthermore, the differential amplifiers tend to sink large amounts of current proportional to speed. The compensation approaches described by Yamatake and Berg are undesirable because the compensation techniques require sacrificing speed for closed loop stability. In addition the op-amp used in the compensation circuit needs to be compensated for stability itself, making the circuit more complex to implement.
FIG. 1 illustrates another approach for providing compensation in a feedback control loop of a switching regulator. Referring to FIG. 1, the output voltage VOUT is coupled to the feedback terminal 15 and further to a voltage divider including resistors R1 and R2. The operation of the feedback control loop in controller 10 is well known in the art. The voltage divider steps down output voltage VOUT and the divided voltage VR is coupled to an error amplifier 20 which compares the divided voltage VR to a reference voltage VRef. Error amplifier 20 generates an error output signal indicative of the difference between voltage VR and reference voltage VRef. The feedback control loop of controller 10 operates to regulate the output voltage VOUT based on the error output of error amplifier 20 so that voltage VR equals voltage VRef.
FIG. 2A is a plot of the loop gain magnitude vs. frequency in log scale for the switching regulator of FIG. 1 without any compensation. The low frequency loop gain is first reduced by a pole associated with error amplifier 20. The gain loss is modified by a zero also associated with the error amplifier. Then, at high frequency, the effect of the double-pole in the LC filter circuit causes a large loss in the loop gain such that the phase shift at unity gain is equal to or greater than 180xc2x0. The feedback control loop of the uncompensated switching regulator of FIG. 1 is unstable unless the gain is substantially reduced.
In the switching regulator of FIG. 1, a capacitor 18 (typically referred to as a xe2x80x9czero capacitorxe2x80x9d) is connected in parallel to resistor R1 of the voltage divider. Capacitor 18 introduces a zero-pole pair in the feedback loop. The location (or frequency) of the zero-pole pair is determined by the resistance of the voltage divider and the capacitance of capacitor 18. For practical resistance and capacitance values, the zero and pole introduced by capacitor 18 are typically located close to each other so that the zero is canceled out quickly by the nearby associated pole. FIG. 2B is a plot of the loop gain magnitude vs. frequency in log scale in the switching regulator of FIG. 1 incorporating zero capacitor 18. Here, the operation of the zero capacitor ensures that the phase shift is less than 180xc2x0 near unity gain. However, the compensation provided by zero capacitor 18 is limited and often does not provide sufficient phase margin at unity gain. For example, at high frequency, zero capacitor 18 shorts out resistor R1, resulting in no or minimal gain loss in the feedback loop. Thus, the compensation provided by capacitor 18 is not effective at high frequency. Also, the voltage divider of resistors R1 and R2 typically provides only a gain loss of 3 dB. The 3 dB gain loss limits the ratio of the pole to zero angular frequency of capacitor 18, and thus, limits the compensation range capable of being achieved by the use of a single zero capacitor 18. The feedback loop of switching regulator of FIG. 1 is susceptible to instability when the switching regulator is subjected to fluctuations in load impedance because of this limited compensation range.
Thus, it is desirable to provide a compensation circuit in a feedback loop of a linear circuit which is capable of providing effective pole cancellation.
An error amplifier circuit includes a differential amplifier with a cascode gain stage and an amplifier. The differential amplifier receives a first input signal and a second input signal and generates an output signal on an output terminal indicative of the difference between the first input signal and the second input signal. The cascode gain stage is coupled to receive the output signal of the differential amplifier and generates a second output signal. The cascode gain stage is biased by a bias current generated by a current mirror. The amplifier receives the second output signal from the cascode gain stage and generates a third output signal. The cascode gain stage is biased by a control signal for causing said current mirror to generate a bias current having substantially constant magnitude over variations in voltage differences of the first input signal and the second input signal.